Cache Memory

The cache memory of the first and second level. In all 486 have an integrated "first-tier cache controller with of 8 or 16 Kbytes. Cache – a high-speed memory, designed for temporary storage code and data. Circulation to the integrated cache occur without wait states, as its performance capabilities suited processor. Through this exchange of information with relatively slow system memory accelerates with authority. The processor does not need to wait for another piece of code or data will come from the main memory area, and this leads to a noticeable increase in the productivity of companies. When lack of cache, such a pause would appear quite frequently. In coming up with an integrated cache, the cpu time is even more central role, as it is often the only type of memory throughout the system, which can work synchronously with the processor.

In a variety of walking up to date processor clock frequency multiplier is used, so they operate at a frequency in a couple of times the system clock frequency board is connected to these processors. For example, the clock frequency of the "333 MHz" is running on a processor Pentium ii, a 5-times have superior clock speed of the motherboard, the same 66 MHz. Since memory is connected to system board, it also can operate only at speeds not exceeding 66 MHz. In such a system from all types of memory integrated cache can only operate at a clock frequency of 333 MHz. Inspected in this sample processor Pentium ii 333 MHz on-chip cache, a total of 32 kb "a 2-separate blocks of 16 kb. If the required data in an integrated cache available, the processor asks for them in the cache memory of the second level or specific to system bus.

In systems Pentium P5 cache in the second level is set on the motherboard and runs at the system board. Eliot Horowitz oftentimes addresses this issue. In the P6 family processors cache second level is set to the processor. In and Celeron processors Heop cache second level operates at a frequency of the processor. The unique Pentium ii processor cache in the second level is working at half the processor frequency.